TUTORIALS


On the afternoon of Monday, October 13th, participants of the EDHPC event will have the opportunity to attend technical tutorials. This page offers information about these tutorials and their technical scope.

ADHA 101 (by ESA, Airbus DS, and Thales Alenia Space)

Introduction

The aim of the Advanced Data Handling Architecture (ADHA) program is to deliver by 2027 a new generation of Platform and Payload Data Handling units, based on standardised, inter-operable and inter-changeable modules from multiple suppliers (multiple sourcing incl. SMEs) that can be integrated in ADHA units by different ADHA unit integrators.

ADHA utilises a standard backplane connector (based on cPCI-Serial-Space, with additional redundancies), with two mechanical form-factors (Eurocard 6U and 3U) and a standard module PA/QA and procurement flow.

Audience
System, Hardware, and Software Engineers working in the data handling domain, with an interest in standardisation of on-board equipment and interfaces.

What will you learn? 

In the first part of the tutorial, we will give a general introduction to ADHA. You will learn more about the structure of the ADHA data pack and gain a deeper understanding of the rationale and applicability of the various requirement specifications and other ADHA documents. Furthermore, you will learn about the different possibilities to propose an ESA R&D activity related to ADHA unit and module developments. In the second part of the tutorial, we will provide you with a detailed overview of the ADHA architecture, including power and communication aspects. Then, in the third part, we will give an in-depth view of various ADHA module designs. Finally, we will present technologies for the thermal management of ADHA units, which are particularly critical for utilising next-generation FPGAs and ASICs.

Speakers:

  • David Steenari (ESA)
  • Julian Bozler, Robin Franz (Airbus DS)
  • Dario Pascucci (Thales Alenia Space)
  • Stephane Lapensee (ESA)

AI-based Spacecraft Pose Estimation on any FPGA (by MathWorks and Adiuvo Engineering)

Introduction

AI is driving autonomy in space, with spacecraft pose estimation playing a key role in docking, navigation, and debris avoidance. Deep learning enables accurate vision-based pose estimation but demands efficient, high-performance hardware. FPGAs and SoCs offer an ideal balance of speed, power, and adaptability for space applications. This work presents a portable AI-based pose estimation solution deployable on any FPGA platform, supporting flexible, real-time operation in diverse mission scenarios.

Audience

  • Engineers who are developing AI algorithms and need to deploy on FPGA/SoC platforms
  • Level: both beginner and expert 

What will you learn?

In part one of the tutorial (by MathWorks), you will learn how to:

  • Verify and validate AI models, if they perform reliably and as intended in mission-relevant pose estimation tasks.
  • Efficiently prototype on FPGA/SoC platforms, and profile and tune for performance.

In part two of the tutorial (by Adiuvo), you will learn how to:

  • Optimize and deploy on ANY FPGA, achieving a balance of low power, compact footprint, and mission-ready reliability. In this tutorial we will be using a Lattice AVANT FPGA.

Speakers

  • Stephan van Beek (MathWorks)
  • Lucas Garcia (MathWorks)
  • Adam Taylor (Adiuvo Engineering)

Radiation Testing (by ESA, Space R3 LLC, and AMD)

Introduction

This tutorial addresses the critical need to modernize radiation hardness assurance for today’s complex FPGAs and SoCs. While traditional methods for predicting component susceptibility are well-established, they are often insufficient for modern, highly integrated devices.

The session will demonstrate how to move beyond conventional external mitigation and testing by taking full advantage of the powerful, built-in features inherent in modern SoCs. We will explore how to leverage on-chip resources—such as embedded processors, system monitors, and high-speed interconnects—to create more effective and efficient radiation hardness assurance strategies. The tutorial covers the fundamental mechanisms of Single Event Effects (SEE) and Total Ionizing Dose (TID) and explores how demands from AI/ML and Functional Safety are shaping new mitigation techniques.

The final section addresses the practical application of these methods in next-generation markets, including telecom, automotive, data centers, avionics, and defense. The tutorial will conclude with a 20-minute roundtable discussion for attendees to engage with the presenters.

Audience

Project managers and FPGA/SoC designers, interested in advanced mitigation techniques, and wanting to learn more about modern Radiation Hardness Assurance techniques.

What will you learn? 

  • Why conventional radiation hardness methods are insufficient for modern, complex SoCs.
  • The fundamental mechanisms of SEE and TID in evolving FPGA and SoC architectures.
  • Strategies for leveraging built-in SoC capabilities (e.g., processors, monitoring blocks) for advanced radiation testing, mitigation, and recovery.• State-of-the-art mitigation techniques shaped by the demands of AI/ML and other high-reliability applications.
  • How to apply these modern assurance methods to systems in the space sector
Speakers: 

  • Maris Tali (ESA)
  • Melanie Berg (Space R3 LLC)
  • Pierre Maillard (AMD)

Hardware Accelerators (by ESA)

Introduction

This tutorial explores how different kinds of parallel accelerators are shaping high-performance computing for space applications, from classical processor designs to emerging processing in memory, AI- and neuromorphic-based approaches.

Audience

Professionals, researchers and students in the aerospace industry who are interested in the application of high-performance computing in space, focusing on parallel computing, hardware accelerators, and space technology.

What will you learn? 

This tutorial explores the advancements in high-performance computing in space using parallel accelerators, including array/vector (SIMD), pipelined, and associative processors, as well as multicore systems with ISA extensions (RISC-V), FPGAs with hard IPs, GPGPUs, processing in memory and neuromorphic processors specialized for high-performance and data-intensive tasks. It provides a qualitative overview of solutions to accelerate algorithms in space by parallelization, highlighting ongoing activities at ESA, identifying challenges, and suggesting potential future trends.

Speakers: 

  • Lucana Santos (ESA)

Satellite Radio Frequency Payloads and Instruments (by ESA)

Introduction

Information will follow soon

Audience

Information will follow soon

What will you learn? 

Information will follow soon

Speakers:

  • Max Ghiglione (ESA)
  • Adem Coskun (ESA)

Neuromorphic AI in Space Tutorials (by BrainChip)

Introduction

In space applications, every milliwatt matters. Satellites rely on ultra-low-power chips to process data on-board, where sending everything back to Earth is often impossible or inefficient. This makes efficient machine learning deployment on embedded hardware not just useful, but essential.

The goal of the tutorials is to show how advanced AI capabilities can be packed into tiny, power-constrained devices, enabling smarter, faster, and more autonomous satellite systems.

Audience

Project managers (particularly part 1) and engineers working on embedded low-power AI applications.
Level: from beginner to expert.

What will you learn? 

In part 1: Akida in Space – Bringing Autonomy, Robustness and Efficient Data Transmission to Space Vehicles, you will learn:

  • Why AI in Space?
  • Why neuromorphic AI in Space?
  • BrainChip Akida IP is the only Event-based AI on the commercial market – IP and silicon
  • Use cases for Neuromorphic Processing in space:o Lunar landingo Docking in spaceo Earth observationo Space Situational Awarenesso Satellite detection (use case OHB Giasaas)

In part 2: Bringing AI to the Edge – End-to-End Machine Learning Deployment on an Embedded Low-Power AI Neuromorphic HW, you will learn:

  • Fetch and prepare a dataset suitable for your target application.
  • Design and train a machine learning model using TF/Keras.
  • Apply quantization techniques to reduce model size and optimize it for embedded hardware.
  • Convert the trained model into a format compatible with Akida hardware toolchain.
  • Export the model as a C source file that can be included and compiled together with your C main application.
  • Integrate the Akida model binary into a baremetal C application running on a STM32 microcontroller.
  • Run inference on Akida ultra-low-power hardware device, demonstrating efficient on-board processing for space-constrained environments such as satellites.

Outline of hands-on tutorial

In the first tutorial, we teach why there is a paradigm shift in Space from purely deterministic classic programming to the use of low power AI in specific use cases. We show the vast improvement in capabilities coming with the use of AI in Space.

In the second tutorial, we demonstrate how to take an ML model from dataset preparation all the way to baremetal deployment on a microcontroller with a hardware accelerator. By the end, you will know how to take an ML project from concept to fully optimized embedded deployment, step by step.

Speakers:

  • Gilles Bézard (BrainChip) – Part 1 & 2
  • Alf Kuchenbuch (BrainChip) – Part 1


ESA Conference Bureau / ATPI Corporate Events

ESA-ESTEC, Keplerlaan 1
2201 AZ Noordwijk, The Netherlands

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