EDHPC 2023

TUTORIALS

On the afternoon of Monday, October 2nd, participants of the EDHPC event will have the opportunity to attend technical tutorials. This page offers information about these tutorials and their technical scope.

Industrial Tutorial about Artificial Intelligence workflows for FPGA & SoC using a Deep Learning Processor (by MathWorks)

Introduction
Artificial intelligence (AI) is everywhere. The space industry is no exception. Automated recognition of lunar craters for moon landings and identification of space junk using imaging could play important roles in securing space safety and advancing space exploration. Deep Neural Networks (DNN) are the most successful solution for image-based object classification, and for most practical applications it requires performant platforms like FPGAs and SoCs.

Designing DNNs for embedded devices such as FPGAs and SoCs is challenging because of resource constraints, the complexity of programming in Verilog or VHDL, and the hardware expertise needed for prototyping on an FPGA or SoC.

Audience
Engineers who are developing AI algorithms and need to deploy on FPGA/SoC platforms
Level: both beginner and expert

What will you learn?
In this tutorial we will explain:

Developing AI models using low code / no code workflows and interoperability with Python based frameworks (TensorFlow and PyTorch).
Verifying and validating AI models.
Prototyping and integrating Deep Learning-based vision applications using a Deep Learning Processor (DLP).
Optimizing model performance on FPGA using compression methods like quantization and pruning.

Outline of hands-on tutorial
This tutorial explores developing a Deep Neural Network (DNN) algorithm leveraging FPGAs for space applications. It covers the deployment of DNN on FPGA platforms to accelerate tasks such as image analysis, object recognition, and data processing. Engineers at all skill levels can learn about optimizing, prototyping, and integrating DNN into FPGA-based systems, enabling efficient and high-performance space-related applications.

Speakers: Stephan van Beek and Pierre Harouimi from Mathworks

Industrial Tutorial (by Lattice)

Introduction
Embedded system solutions play an important role in FPGA system designs for Space allowing designers to develop software for processors in FPGAs, provides flexibility and in-orbit programmability to implement distributed architectures via system bus.To develop an embedded system on an FPGA, user needs to design the System-on-Chip (SoC) with an embedded processor, develop system software on the processor and implement the complete architecture design in the FPGA.

Audience
The intended audience for this hands-on tutorial includes embedded system designers, embedded software developers and FPGA designers.

What will you learn?
In this hands-on tutorial you will learn the basics of LATTICE Propel™ and Radiant™ tools while developing a complete reference design.
Lattice Propel™ helps users develop a system with a RISC-V processor, SpaceWire IP, and a set of embedded tools.
Lattice Radiant™ helps the FPGA designer implement the developed architecture design.
No prior knowledge of LATTICE Propel™ and Radiant™ is required. Lattice will provide all required hardware and software for this hand-on tutorial.

Outline of hands-on tutorial
The tutorial will guide you through the development of a reference design:

How to build an embedded design with RISC-V and SpaceWire
How to develop the software for the processor subsystem
How to implement the architecture design in the FPGA
How to debug the system using the Propel™ environment

Note: Installation of software before attending the tutorial
To prepare for the hands-on tutorial, you need to install LATTICE Propel™ and Radiant™ on your computer prior to the event. LATTICE Propel™ and Radiant™ installation and free license will be provided upon completing your registration for the tutorial.

Tutorial on Radiation Effects on On-Board Data Handling and Data Processing Systems (by ESA and industry)

Introduction
The tutorial will cover various aspect related to radiation testing and radiation mitigation on On-Board Data Handling and Data Processing Systems. We will cover topics on digital technologies, radiation testing planning and execution, Radiation Hardness Assurance, mitigation techniques and ESA Mission Classification. Special focus will be on complex devices often used in Data Handling and Processing Systems.

Audience
All on-board data handling and data processing professionals interested in learning more about different aspects of radiation testing and radiation mitigation in hardware flying on satellites today and in the future.

What will you learn?
The tutorial will cover various aspect related to radiation testing in the first part and radiation mitigation in the second part. The radiation testing portion of the tutorial will start with an overview of digital and analogue technologies, focusing on the different options for the space market from David Merodio and Richard Jansen (ESA). Then, we will get a thorough overview of the basic mechanisms of radiation-induced faults in complex devices with an emphasis on COTS component by Dr. Indranil Chatterjee (Airbus). You will learn the basic metrics for setting up successful Single Event Effect (SEE) test campaigns, running the tests and analysing the test data. Finally, you will about the necessity of updating our radiation hardness assurance methods for better characterization of today’s complex system applications by Melanie Berg (Space R2 LLC). The second half of the tutorial will focus on different aspects of radiation effects mitigation in complex COTS devices on both module and component level by Kostas Marinis and Lucana Santos (ESA). Finally, we will learn about the new ESA mission classification, including tailoring of the Q branch and its implications on the different radiation testing requirements including some words about ESA experiences by Viyas Gupta (ESA).

Speakers: David Merodio (ESA), Richard Jansen (ESA), Dr. Indranil Chatterjee (Airbus), Melanie Berg (Space R2 LLC), Kostas Marinis (ESA), Lucana Santos (ESA), Viyas Gupta (ESA)

Tutorial on Satellite Radio Frequency payloads and Instruments – Overview and challenges for data and signal processing (by ESA)

Introduction
The implementation of radar and telecommunication requirements into digital back-end technology demands an increase in bandwidths, more powerful digital data processing, and higher speed interfaces.
It is nowadays common to see Space-qualified data conversion devices and FPGAs, HSSL capable of converting signals in the GHz range, processing them and transferring them for transmission or further processing of the received data. This allows to move more functions to digital components and an improvement of flexibility from a system perspective.

This tutorial provides and overview of the most employed hardware architectures in radar and telecommunication payloads. It provides an explanation of the major design trade choices that are typically done when defining a radar system, taking into account the constraints from the existing hardware capabilities as well as missions requirements.

The first part of this tutorial will describe the end to end architectures of telecommunication payload, focusing on new requirements related to digital beamforming, regenerative processing and 5G protocols.

The second part of this workshop will describe the end to end architectures of radar payloads, focusing on new requirements for upcoming missions.

Audience
The intended audience for this workshop is space industry professionals that want to understand or reflect on the impacts of digital processing functions in radio frequency payloads. The workshop is aimed in particular to suppliers of equipment and components interested in discussing requirements for upcoming missions.

What will you learn?
The tutorial will give an overview of end-to-end architecture for radio frequency payloads and highlight the design drivers in digital processors.

Outline of hands-on tutorial
This tutorial explores new trends in on-board processing for Radio Frequency Payloads. The main areas of development for upcoming Synthetic Aperture Radar and Telecommunication missions are presented and discussed.

Speakers: Salvatore D'Addio (ESA), Max Ghiglione (ESA)

Overview of On-Board Processing Technologies for future Space Missions (by ESA)

Introduction
The tutorial will start by introducing the concept of ESA mission class, followed by a presentation showing the mostly commonly used devices in ESA payloads, onboard computers (OBC) and instruments control unit (ICU). While rad hard parts may not need radiation mitigation techniques at board / equipment level, rad tolerant device on the contrary may require extra care to mitigate “single failure interrupt” (SEFI). SEFI mitigation techniques will be addressed in this presentation.

Audience
This tutorial is dedicated to young professionals and companies with limited experience related to space onboard processing technologies. The tutorial will provide the audience with a non-exhaustive but broad overview of the technologies used in ESA class 1,2,3, missions.

What will you learn?
Participants will learn about ESA mission class differentiation. Participants will learn about FPGAs, SoC FPGAs and processors used or planned to be used in ESA class 1,2,3 missions. Attendees learn about SEFI mitigation techniques.