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Session 7: Developments in Devices and IPs for On-Board Processing

Day 3 - Advances in Data Processing Devices and Equipment
Wednesday, June 16, 2021
1:00 PM - 2:40 PM


Mr. David Steenari

Survey of High-Performance Processors and FPGAs for On-Board Processing and Machine Learning Applications

1:00 PM - 1:20 PM

Abstract Submission

Over the last years there has been an accelerated increase in the requirements for On-Board Processing (OBP) for satellite on-board systems. These requirements include higher instrument data rates and the introduction of new techniques such as on-board machine learning inference (OBMLI). Outside of a demand for increased computational performance, the need for in-flight re-configurability, as well as shortening development time and cost are increasingly driving the selection of processors and FPGAs in the design of on-board systems.

To address these needs, several COTS processor and FPGA devices have been proposed for the use in space applications. While providing superior performance compared to devices specifically designed for radiation environment, the qualification status and lack of openly available radiation data may be prohibitive for the use of COTS devices in certain applications.

In this work, a survey of both COTS and RHBD devices supporting high-performance OBP that are currently used or have been proposed to be used in future missions are presented. The survey presented includes device parameters such as the relative performance, qualification status and the availability of radiation test results. Devices included in the survey are: FPGAs, MPSoCs, multicore processors, manycore processors, GPUs, dedicated AI/ML accelerators, etc.

Finally, an overview of the availability of machine learning tools for the listed devices is also presented. It is shown that several available devices targeting space applications, offer their users tools for the development and deployment of machine learning algorithms.

The work has been carried out partially internally at ESA, and through the on-going TRP activity "FOPIEA" (Future On-board Processing Information Extraction Algorithms). The goal is to have a tentative list of devices that can be used in future ESA missions for IOD purposes. Part of the work has already been provided as input for the ESA COTS initiative working group.
Mr. Ganry Nicolas
Microchip France

From Commercial off-the-Shelf (COTS), Radiation-tolerant to Radiation-hardened Devices, Today’s Unique Scalable Microprocessors (MPUs) and Microcontrollers (MCUs) with associated companions’ devices benefit Space System Designs

1:20 PM - 1:40 PM

Abstract Submission

This presentation will focus on the Commercial-off-the-Shelf (COTS) to radiation-tolerant model applied to a wide range of MCUs and scalable ARM M7 System on Chip (SoC) solutions and radiation-hardened devices, to answer to space market challenges in terms of schedule, cost savings and reliability. This unique approach benefits from widely-deployed software and hardware ecosystems and is, today, enabling a wide range of space applications including data handling, remote control and computation. Product overview and application use cases will be presented on Microchip’s SAMV71Q21RT radiation-tolerant MCU and SAMRH71 radiation-hardened MPU, both ESCC-qualified and based on ARM Cortex M7 core and SoC architectures.

With its new SAMRH707 device, a radiation-hardened MCU developed with the European Space Agency (ESA), Microchip took a step forward in the scalability trend of integrating analog functions including Analog to Digital Converter (ADC), Digital to Analog Converter (ADC), and Non Volatile Memory (NVM) in yet smaller device packages. Radiation performances with SEE and TID are the major parameters differentiating COTS, radiation-tolerant and radiation hardened solutions enabling full adaptation to the targeted space missions. With ceramic QML equivalent/ESCC qualified and plastic high-reliability qualified versions, those highly integrated devices help to offset costs and time-to-market in space systems.

This presentation will discuss the different proposed quality flow and demonstrate pin distribution compatibility between devices, to facilitate PCB design and the transition from plastic to ceramic packaging. This presentation will also cover other companion devices around space processing solutions from Microchip contributing to deployment in space of Ethernet, reprogrammation of FPGAs, motor controls, CAN FD communication and telemetry management for example On top of new product information, demonstration use cases of implementation with related hardware and software will be presented.

This presentation will focus on aerospace and defense activities in Europe, particularly technology developed by Microchip’s group in Nantes. For decades, Microchip has provided one of the industry’s most comprehensive space product portfolios of radiation-hardened and radiation-tolerant solutions that include high-performance MCUs, MPUs, FPGAs, memories, communication interfaces, frequency and timing solutions, mixed-signal ICs, custom power supplies, diodes, transistors and RF components. With product development activities and a qualified supply chain in Europe, Microchip is key contributor to the European space ecosystem, delivering European and ESCC-qualified solutions.

Mr. Olivier Notebaert
Airbus Defence And Space

NG-Ultra validation and on-board processing board development

1:40 PM - 2:00 PM

Abstract Submission

The need for a significant increase of the on-board data processing performance/power ratio with higher flexibility in space systems is asserted for several years already. The assigned targets for future space data processors led to the development of the NG-Ultra processing component through several European Research and Development programs supported by major institutional and industrial stakeholders. This device is a key building block for achieving the European objectives of high competitiveness and technology non-dependence in future space systems.
The NanoXplore's NG-Ultra is a Rad-Hard Multi-Processor System on a Chip (MPSoC) embedding 4 cores Arm® and a very large FPGA matrix with pre-developed generic functions for spacecraft data-handling. It provides room to embark more processing functions as needed by user applications. Major milestones of the NG-Ultra development have been achieved in 2020 in particular with the successful production of the first samples components. Evaluation boards have been delivered to Airbus Defence and Space to validate the design and provide feedback also on the associated development tools. In parallel to these bring-up activities, the next generation computer development has started, built on NG-Ultra component as its processing core. It follows the Advanced Data Handling Architecture modularity requirements with the objective to provide a high performance processing function covering all kind of space applications for the next On Board Data Processors generation.
The presentation will provide an overview and update on these activities, together with a perspective for the utilization of the NG-Ultra in future on-board processing products.


Mr. Thomas Guillemain
Teledyne e2v

“New Space” use cases permitted by Radiation Tolerant Space qualified Compute intensive processors, memories and modules solutions from Teledyne e2v

2:00 PM - 2:20 PM

Abstract Submission

While seeking the highest amount of protection and reliability in Space (against harsh environments, radiations) has nailed down for a long time the computing performances of Space systems towards low levels versus commercially available devices, some recent use-cases would probably push this into the opposite direction, i.e. much higher amounts of computing capabilities with lower but decent tolerance to Space constraints. Therefore, New Space systems’ designers may think the specifications of their systems differently, with new compromises. Yesterday’s requirements for high protections / low CPU may be transformed into mitigating the protection levels for a disruptive amount of CPU.
Teledyne e2v has chosen for long to offer radiation tolerant Gigahertz class compute intensive devices for Space payloads and platforms. Recently, the most powerful CPU for the Space market was introduced, a Quad ARM® Cortex®-A72 (30,000 DMIPS), as well as high-speed high density DDR4 memory (4GB - gigabytes).

A substantial amount of radiation testing campaigns on these Teledyne e2v Space parts have allowed to characterize all of them against radiations, to provide reports, guidelines, mitigation schemes to their users.
Those characterizations against radiation effects are perfectly complementing the inherent Space quality level and robustness of Teledyne e2v parts (QML-Y or ECSS/NASA grades).

This paper presents the radiation testing techniques, results and qualification levels of Teledyne e2v’s high capability compute intensive components.
Results on LS1046-Space (Radiation Tolerant Quad ARM Cortex-A72), DDR4T04G72 (Radiation Tolerant high speed compact 4GB DDR4), and Qormino® QLS1046-4GB-Space (compact computing module embedding LS1046-Space & DDR4T04G72 components) will be presented. These results highlight that latest campaigns on TID and SEE (SEU, SEFIs) performed by Teledyne e2v allow any designer of Space systems to consider those devices.

In order to better understand the level of computing capabilities from Teledyne e2v components, and how their usage allow to contemplate very modern use cases for Space, this paper also presents example of applications that can be considered with such components. A specific focus, is made on the preliminary results obtained on a project aiming at using Qormino for Artificial Intelligence (AI) in Earth observation applications. In particular, benchmark activities were performed to evaluate the Qormino performance on classical neural networks, and compare it with standard components. Some extracts of this benchmark study are presented, in order to outlook what the new space applications may foresee and benefit from safe Space qualified compute intensive parts.
Mr. Barry Kavanagh
O.C.E. Technology Ltd

The hisaor chip - Analysis of a new system-on-chip that combines advanced neural network and digital signal processing with multiple interfaces, radiation tolerance, and low power consumption.

2:20 PM - 2:40 PM

Abstract Submission

The design of a device to support data processing on a satellite must provide good radiation tolerance, low power consumption, the ability to interface with a range of different data sources, and high throughput digital signal and neural network processing. It should also be compatible with the main software development platforms, in particular those used in artificial intelligence.
The new hisaor system-on-chip from O.C.E. Technology addresses these requirements, balancing them in a way that offers an effective solution across a wide range of potential applications, in particular those that use neural network processing. Our paper will describe and explain the choices made in arriving at the hisaor design and provide an analysis of its performance.
The hisaor design includes an Artificial Intelligence unit with 8 GPUs and 8 Neural Network processors sharing a common cache. The main system processor is a quad core ARM Cortex-A9, each core with 32 KiB L1 instruction and data caches, a 512 KiB Level 2 cache is shared by all four cores. High band-width on-chip memory includes 1 MiB SRAM and 2 x 32 KiB boot ROMs, and a range of external memory types can be connected. ECC is supported.
At its 1 GHz maximum clock frequency hisaor can provide 64 GFLOPS and for fixed point calculations 12 TOPS. Maximum power consumption is 6 Watts.
As it is expected that many applications will involve processing images, hisaor includes a range of media processors, including H264/H265/JPEG2000 encoders/decoders. Camera Link and MIPI interfaces are provided, other interfaces include 1553B, CAN, BT1120, SPI, USB, Gigabit Ethernet, and others.

hisaor is compatible with OpenCV, OpenVX and OpenCL. Its neural network processing units support convolutional and other approaches to neural network processing and are compatible with the standard approaches to machine learning and neural network processing, including the Caffe framework and TensorFlow.

As well as describing the reasoning behind the design of hisaor our paper will present performance metrics based on a number of applications and outline possible future developments in the design.


Session Chairs

Roberto Camarero

Roland Laulheret