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Session 8: New Equipment for On-Board Processing

Day 3 - Advances in Data Processing Devices and Equipment
Wednesday, June 16, 2021
2:55 PM - 4:15 PM


Mr Anandhavel Sakthivel
Cobham Gaisler AB


2:55 PM - 3:15 PM

Abstract Submission

Cobham Gaisler and RUAG Space are developing a high-performance Single-Board Computer (SBC). The SBC provides substantial processing capability along with an extensive set of memories and redundant interfaces to support the needs of current and future OBC, data handling platforms, and payload data processing. The SBC is developed following the CompactPCI Serial Space backplane standard (CPCI-S.1 R1.0).

The processing capability for the SBC is provided by the GR740 Quad-Core 32-bit LEON4FT SPARC V8 processor along with the Microsemi RTG4 radiation tolerant FPGA. The RTG4 brings the DDR2 memory and high-speed serial link (HSSL) capability to the SBC. The glue-logic required to be compatible with the CPCI-S.1 R1.0 standard are also implemented in the FPGA. More than 70 % of the LUT/Flip-flops and 100 % of the math blocks are still available in the FPGA for application specific developments and implementation of accelerator functions.

With the available processing capability, the following applications are identified as potential use cases for the SBC:
• Image processing and selection of valuable data for earth observation or similar missions
• Visual navigation for critical docking and lander missions, e.g., debris removal, satellite life-extension and lunar and mars missions
• Object identification tracking for surveillance missions
• Centralized payload control and data handling for multiple instruments

The SBC is accompanied by boot software (GRBOOT) and device drivers. The GRBOOT boot software is responsible for taking the GR740 from system reset state to the execution of multi-processor mission application software. The boot SW consists of three parts, multi-processor initialization, processor self-tests, standby mode and application loader. The implementation of the GRBOOT represents a tailoring of the ESA SAVOIR-GS-002 specification "Flight computer initialization sequence". A high-quality implementation of drivers for: GR740 CAN (GRCAN), PCI host (GRPCI2) and SPI (SPICTRL) controllers are available for the GR740 SBC application developer. The drivers are compatible with RTEMS-5 SMP.


Dr. Jochen Rust
Dsi Aerospace GmbH

High-Performance Data Processing Unit for Space Applications

3:15 PM - 3:35 PM

Abstract Submission

Efficient data and signal processing is a key enabler in several space-related application areas. Within the last years complex applications like machine-learning-based earth observation, satellite-based quantum communications or 5G non-terrestrial networks have become very popular, but require a significant increase of the currently available processing resources. On the other hand, also a strong demand for an effective reduction of the production costs is recognizable. A promising idea to achieve these challenging goals is to go for a distinctive standardization of space components and interfaces. By this measure the scalability and re-usability of existing designs can be significantly improved, which are key parameters for the cost-efficient production and deployment of novel space hardware.

To compete with these challenging goals, we present DSI's high-performance data processing unit (HPDPU): a novel powerful PDHU for the efficient data processing of next generation space applications, designed as a compact (form factor 6U) but also lightweight (~ 800g) board. Core of this platform is the novel Xilinx Kintex Ultrascale FPGA device that is available as a commercial (XCKU060) and a radiation hard (XQRCU060) variant and provides an extremely high number of device resources, e.g. logic cells, DSP slices, block RAM, etc. at reasonable energy costs. For high-speed serial data transmission, 32 gigabit transceiver channels (GTH) are available.

In order to achieve the desired re-usability, the cPCI Serial Space (cPCI-SS) backplane connector is considered which enables the deployment of a modular computer system. Typically, cPCI-SS is designed to manage two system boards, seven peripheral boards, a power supply and a shelf controller board via the backplane. For high-performance data transfer and configuration, the HPDPU provides 2 PCIe, 2 Ethernet and 2 SpaceWire interfaces.

For further functionality and modularity increase, the HPDPU also possesses FMC-based mezzanine connectors. By this measure, the same basic platform can be adapted to numerous different applications simply by adding an application-specific extension card to the HPDPU motherboard.

For supervision of the power supply and FPGA behavior, a radiation tolerant supervisory system monitor IC is considered, providing essential reset, watchdog as well as power-up/power-down functionality. In order to guarantee correct boot loading and (re-)configuration, a sophisticated radiation hardened system controller is implemented. In addition, a 256 MiByte NOR-Flash-based configuration memory for periodic scrubbing is taken into account, running in TMR. For the storage of user data or payload, 8 GiBit DDR3 SDRAM with a 16 bit data bus is provided. To achieve high reliability, a Reed-Solomon Code RS(12,8) ECC block is considered that is capable to detect and correct symbol errors on the data bus.

A more comprehensive description of the HPDPU comprising a detailed explanation of all of its features will be given in the full paper.


Dr. Björn Fiethe
IDA TU Braunschweig


3:35 PM - 3:55 PM

Abstract Submission

Current and future space missions demand sophisticated on-board data processing functionalities, while low resources consumption remains a constraint. Thus, in-flight reconfigurable architectures are mandatory. Using dynamically reconfigurable FPGAs allows enhancement of on-board processing with unprecedented levels of flexibility, enabling the adaptation of the system regarding functional and fault-tolerance requirements, subjects to change during mission lifetime. Different operational modes can be served, especially for sharing of complex algorithms on limited FPGA resources.

For instrument control and data processing of the PHI instrument on the Solar Orbiter mission (SO/PHI), we have partially adapted results of the ESA study for a Dynamically Reconfigurable Processing Module (DRPM) and implemented a flexible, in-flight reconfigurable, power efficient, and radiation tolerant processing module based on Xilinx Virtex-4 SRAM-based FPGAs. While these and the rad-hard Virtex-5 FPGAs have been used for many current space missions, they provide only insufficient logic resources and embedded memory for future usage. Instead, the Kintex Ultrascale XQRKU060 has become a state-of-the-art rad-tolerant FPGA implementation. As the Xilinx Zynq Ultrascale+ shows, integration of dedicated processors is presently used already for military and commercial space applications.

After having demonstrated the usage of in-flight reconfigurability for SRAM-based FPGAs on SO/PHI, we have developed a universal platform for high performance on-board data processing, based on cPCI Serial Space standard and state-of-the-art Xilinx Zynq Ultrascale+ MPSoC device on a single board (3U). The cPCI Serial Space standard guarantees the modular extensibility of the system. The board provides two banks of 64 Gibit DDR3-SDRAM memory and TMR NOR-Flash for configuration and SW code, together with various interfaces, like PCIe, SpaceWire, and Ethernet. Optionally, this could be expanded to control NAND-flash mass memory or implemented with an EV-MPSoC including video codec to enable compression and recording of data streams from video cameras.

This module is being used within the H2020 project S4Pro, which investigates how to combine state-of-the-art industrial computing technologies (namely Xilinx Zynq UltraScale+) and space qualified embedded computing platforms in order to optimize the data processing chain and support the next generation of data intensive missions. The approach targets not only the enhancement of technology transfer to nano- and small satellites, but also the enabling of institutional satellite missions that rely on operational tasks with very high bandwidth, processing, and storage requirements. Hence, the Zynq Ultrascale+ is used for on-board data elaboration, e.g. for SAR and multispectral imaging applications, due to its strong interfacing capabilities and integrated software processing units based on the ARM A53 core architecture.

Additionally, we are implementing a derivate with similar cPCI Serial Space interfaces using the Xilinx XKU060 (XQRKU060) FPGA. Especially for different types of reconfiguration and scrubbing, a system controller connector is available to connect a special reconfiguration engine. This can be used also to perform fault injection into the FPGA and thus exercise FDIR aspects. Based on this, we are involved in a design study for the Lagrange PMI instrument DPU as follow-on of SO/PHI. In the full paper, we will present more details of our modules and applications.


Mr. Paul Bajanaru
GMV Innovating Solutions SRL


3:55 PM - 4:15 PM

Abstract Submission

GMV is in charge of developing the GNC subsystem of HERA mission, currently going through Phase C. At the end of Phase A of the mission, it was identified the lack of any dedicated avionics platform for the implementation of hardware accelerated image processing algorithms required by the spacecraft autonomous navigation strategy. The hardware solution proposed by GMV in order to whitstand the demanding mission GNC requirements is in the form of a dual purpose avionics processing board for image processing and interface control (including management of interfaces with OBC and in-flight reprogramming): HERA Image Processing Unit (HERA IPU).
The main drivers of HERA IPU design were the nominal and redundant SpaceWire I/F with the HERA S/C OBCs, and the ability to accommodate and accelerate in hardware the required image processing algorithms having as input images taken by a navigation camera.
The HERA Image Processing Unit provides isolation of Image Processing Function and Interfaces Function, as it is relying on a two FPGAs architecture, with allocated external volatile and non-volatile memories. It is composed of one small and reliable European FPGA with rad-hard equivalent, BRAVE NG-Medium, dedicated to interfaces control and monitoring and the other one is a powerful FPGA to perform as computer vision co-processor. The current Processing FPGA is the Virtex-5 VFX130T, with its space equivalent component the high-density rad-hard V5QV FPGA.
The SpaceWire interfaces allow TM/TC exchange between HERA IPU and two devices/instruments using nominal and redundant SpaceWire links (nominally 2 on-board computers, but the scenario can be adapted to only one on-board computer and one navigation camera). The design and development of the computer-vision algorithms for HERA IPU are facilitated by the architectural design of the processing FPGA code, which provides an internal interfacing wrapper to integrate the required image processing module satisfying a client-consumer simple interface. HERA IPU also includes pre-processing functions for the image received from navigation camera.
The two FPGAs included by HERA IPU allow flexibility and many options for the design and implementation of complex functionalities, such as high-data rate interfaces management and hardware accelerators. Different computer-vision accelerators which are not used in the same moment of time can be used during the mission by replacing bitstreams in the processing FPGA in-flight to save a potentially needed second FPGA unit.
The image processing algorithms envisaged by HERA GNC strategy depend on the phase of the mission, and include as minimum: LAMB (maximum correlation with a lambertian sphere – providing the position of the asteroid in the Field of View of the camera) and RelNav Feature Tracking (significant features are extracted from the navigation image, and afterwards compared with the features extracted from previous image in order to find their correspondence).
The unit was validated as TRL 4/5 Elegant breadboard, while the validation of a fully scaled Engineering Model is expected to be finished mid 2021. The roadmap towards flight hardware is deemed with high probability of success, as all the electronic components selected for the engineering model have space qualified correspondents.


Session Chairs

Thomas Firchau

Benoit Leroy