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Session 10b: Advances in On-Board Processing Architectures

Day 4 - On-Board Processing Architectures
Thursday, June 17, 2021
2:45 PM - 3:45 PM


Mr. Patrick Kenny
Deutches Zentrum für Luft- und Raumfahrt

Parallelizing On-Board Data Analysis Applications for a Distributed Processing Architecture

2:45 PM - 3:05 PM

Abstract Submission

Satellite-based applications produce ever-increasing quantities of data, challenging the capabilities of existing telemetry and on-board processing systems, especially when results must be transmitted quickly to ground.
The Scalable On-Board Computing for Space Avionics (ScOSA) platform contributes the processing capability necessary to perform such computationally intensive analysis on-board. This platform offers a high-performance on-board computer by combining multiple commercial off-the-shelf processors and space-grade processors into a distributed computer. Middleware ensures reliability by detecting and mitigating faults, while allowing applications to effectively use multiple, distributed processors.
The current work aims to demonstrate the use and advantages of utilizing the data-flow programming paradigm supported by the ScOSA platform to provide high-throughput on-board analysis. This enables rapid analysis even for applications requiring high frame rates, high resolutions, multi-spectral imaging or in-depth processing.
The On-Board Data Analysis and Real-Time Information System (ODARIS) is used to demonstrate this method. ODARIS is a system for providing low-latency access to satellite-based observations, even when large quantities of sensor data are involved. By performing on-board processing of the data from the satellite-borne instruments, the amount of data which must be sent to ground is drastically reduced. This allows the use of low-latency telecommunication-satellite constellations for communicating with ground to achieve query-response times of only a few minutes. The current application combines an Earth-observation camera with AI-based image processing to provide real-time object detection.
In the data-flow driven implementation of ODARIS on the ScOSA platform, images are captured by a camera and sent to any of several processors for the computationally intensive image processing. This allows multiple images to be processed in parallel by as many processors as are available, while avoiding the need to divide each image across several processors. The results are transferred to an on-board database from which queries can be served asynchronously.
The system will be tested in configurations with one, two and three processors and the resulting image throughput presented. Testing is performed on a ground-based prototype system using pre-recorded images.
This paper presents the necessary details of the underlying ScOSA and ODARIS systems as well as the implementation of the objection-detection algorithm using a parallelized, data-flow model. The results of executing the system using a variable number of processors are presented to demonstrate the improvement in image throughput and its potential application to other computationally-intensive tasks.


Mr Joaquin Espana Navarro
Cobham Gaisler Ab


3:05 PM - 3:25 PM

Abstract Submission

Cobham Gaisler, in collaboration with Ubotica Technologies, the National and Kapodistrian University of Athens, and QinetiQ Space, is developing a High-Performance Compute Board (HPCB) within the European Space Agency GSTP activity “FPGA Accelerated DSP Payload Data Processor Board”.
Compared to existing technology, the HPCB platform will provide more computational resources onboard spacecrafts to process high bit-rate payload data before downlink, thus reducing bandwidth requirements and improving reaction times of space systems.
The target applications include on-board payload processing for optical and radar instruments, as well as visual navigation. The board can be integrated in payload data handling units, mass-memory and/or on-board computer to enable functions such as high-performance on-board image processing, machine vision and standard CCSDS image compression. The board design is optimized for the data handling and processing of multiple instruments simultaneously.
The architecture combines up to three Vision Processing Units (VPUs, Intel Movidius Myriad 2), a high-capacity FPGA (Xilinx Kintex Ultrascale XCKU060), and a radiation-tolerant microcontroller (Cobham Gaisler GR716), in order to create a reliable system solution for space applications that matches what is available in the commercial domain in terms of performance and functionality. The use of three VPUs and the parallel cores within each VPU leads to the high performance needed for image/application processing.
The architecture targets a 6U by 160 mm Payload Module implemented according to the OpenVPX standard (VITA 65). The main board contains the microcontroller and the FPGA and supports the use of up to three VITA 57.1 FMC mezzanine cards. Each mezzanine contains a VPU and its associated power and memory components. The VPUs can be operated in parallel for maximum performance or redundant configurations.
The main front-panel interfaces to operate the platform are four SpaceFibre links and two SpaceWire links. The SpaceFibre links nominally operate at 3.125 Gbps and are routed to the high-speed transceivers of the FPGA, whereas the SpaceWire links run at 100 Mbps and are routed to both FPGA and microcontroller via a cross-point-switch. Backplane interfaces are adapted to the OpenVPX standard and include SpaceWire for control and SpaceFibre for data. The board can also be operated stand-alone, equipped with debug links such as USB and JTAG intended for lab usage.
The main board contains 2 SPI flash memories with the configuration files for the microcontroller, the FPGA and the VPUs. Additionally, it includes 2 DDR3 SDRAMs which operate as the working memory of the FPGA. This allows to buffer large amount of input images before they are processed by the VPUs. Each VPU has a dedicated 4GB DDR3 acting as its working memory.
The HPCB is accompanied by software images for both the VPUs and the supervisor microcontroller. The VPU software exposes a unified API for image pre-processing functions and for Neural Network inference. End users can further expand the functionality of the board by procuring or developing new software for the VPUs.
The integration testing of all hardware and software module is on-going and the HPCB is planned to be released in Q2/Q3 2021.


Eng. Gianluca Giuffrida
University Of Pisa

Satellite Instrument Control Unit with Artificial Intelligence engine on a Single Chip

3:25 PM - 3:45 PM

Abstract Submission

As the number of earth observation missions increases, and so does the number of images acquired by satellites, the need of optimizing on-board mass-memory allocation and data transmitted to ground becomes more and more important, as both are limited resources. Currently, large players in the space industry are still designign Instrument Control Units which are largely customized so, once developed, they can only be exploited for the single mission they have been designed for. On the other hand, the unavailability of commercial flexible, programmable and space-qualified solutions ready to be integrated keeps small-medium enterprises out of this market, since mostly large-scale integrators have the resources needed to undertake custom development at unit level.
The Instrument Control Unit with Artificial Intelligence Engine System on Chip presented in this work aims at changing the rules of image/data handling and processing on-board satellites, overcoming the downsides of the current scenario both at the technological and industry level.
The core of the proposed system is a soft-programmable hardware GPU, referred to as FGPU from now on, which integrates an artificial intelligence engine able to deliver an innovative fully programmable data handling and data processing system on a chip. The envisaged embedded system can analyse and process the data acquired directly on-board, using artificial intelligence and computer vision algorithms, to discharge unwanted data and transmit only the meaningful ones. It is also fully re-configurable, to allow for the retargeting of earth observation missions as monitoring needs change, even temporarily.
At a broader industry level, the commercial availability of such a solution would translate into an enlarged room for Small Medium Enterprises for leading independently space missions and projects, hence wider business opportunities in the space domain.
The adopted approach leverages three highly innovative, open-source components at the advanced technology readiness level: the RISC-V processor as a command-and-control platform; the FGPU provided by B-TU as hardware accelerator for computer vision and artificial intelligence algorithms; and the SpaceFibre/SpaceWire as communication module. The three components are integrated into a single modular, flexible, and powerful embedded architecture on a single chip, and more in particular on a space-grade FPGA.


Session Chairs

Thomas Firchau

Patricia Lopez Cueva
Thales Alenia Space France