A High-Performance RTL Implementation of the CCSDS-123.0-B-2 Hybrid Encoder on a space-grade SRAM FPGA
| Monday, September 21, 2020 |
| 3:26 PM - 3:50 PM |
Speaker
Attendee56
National And Kapodistrian University Of Athens
A High-Performance RTL Implementation of the CCSDS-123.0-B-2 Hybrid Encoder on a space-grade SRAM FPGA
Abstract Submission
Nowadays, hyperspectral imaging is recognized as a cornerstone remote sensing technology. The latest high-resolution and high-speed space-borne imagers have brought an explosive growth in data volume and instrument data rates in the range of several Gbps. This competes with the limited on-board storage resources and downlink bandwidth, making hyperspectral image data compression a mission critical on-board processing task. Due to the high data volume reduction often needed to meet spacecraft downlink bandwidth requirements, lossy compression is becoming increasingly important. In this context, the Multispectral Hyperspectral Data Compression (SLS-MHDC) Working Group of the Consultative Committee for Space Data Systems (CCSDS) standardized the new Issue 2 "Low-Complexity Lossless and Near-Lossless Multispectral and Hyperspectral Image Compression" standard CCSDS-123.0-B-2. This new Issue 2 extends Issue 1, incorporating support for low-complexity near-lossless compression, while retaining compatible lossless compression capabilities, where “near-lossless” refers to the ability to perform compression in a way that limits the maximum error in the reconstructed image to a user-specified bound.
A key feature of CCSDS-123.0-B-2 is the new Hybrid Encoder option. At high bit-rates, the Hybrid Encoder encodes most samples using a family of codes that are equivalent to those used by the Sample-Adaptive Encoder of Issue 1, and thus has nearly identical performance. However, at low bit rates it has substantially better performance than the Issue 1 entropy encoders. For example, the Sample-Adaptive Encoder of Issue 1 cannot reach bit-rates lower than 1 bit-per-sample due to design constraints, while the Block-Adaptive Encoder may, but at a non-negligible bit-rate overhead.
The Hybrid Encoder option specified in CCSDS-123.0-B-2 is a modified version of the one originally used by the NASA FLEX entropy coder so that decoding proceeds in reverse order. This permits a more memory-efficient implementation than FLEX’s original coder, which was based on an interleaved entropy coding approach. The Hybrid Encoder includes codes equivalent to the length-limited GPO2 codes used by the Sample-Adaptive Encoder but it is augmented with an additional 16 variable-to-variable length “low-entropy” codes to provide better compression of low-entropy data. Such low-entropy data become more prevalent as increasing predictor quantization step sizes are used. The Hybrid Encoder adaptively switches between high and low entropy encoding methods on a sample-by-sample basis, using code selection statistics similar to those used by the Sample-Adaptive coder. A single output codeword from a low-entropy code may encode multiple samples, which allows obtaining lower compressed data rates than can be produced by the Sample-Adaptive Entropy coder.
In this contribution, we introduce a high-performance hardware implementation of the CCSDS-123.0-B-2 Hybrid Encoder targeting space-grade SRAM FPGA technology, described in portable VHDL RTL. The proposed Hybrid Encoder RTL architecture comprises 6 components at the top structural level: 1) an Adaptive Code Selection Statistics unit, 2) a High/Low Entropy Decision unit, 3) a High Entropy Encoder unit, 4) a Low Entropy Encoder, 5) a Codeword Combiner and 6) a Variable Length Code Packer unit. The proposed architecture achieves 1 sample per cycle when the high-entropy encoding method is selected and multiple cycles per sample when low-entropy coding is selected, while the deep pipeline enables very high clock frequencies. Moreover, the proposed architecture exploits the systolic design pattern to provide modularity and latency insensitivity in a elastic pipeline.
The implementation of the proposed architecture on a Xilinx Kintex Ultrascale XQRKU060 space-grade SRAM FPGA achieves state-of-the-art throughput performance of up to 354 MSamples/s (5.66 Gbps @ 16bpp) while occupying approximately 2.85% of device LUTs and 0.1% BRAMs of the FPGA resources. To the best of our knowledge, this is the first implementation of the CCSDS-123.0-B-2 Hybrid Encoder Implementation a space-grade SRAM FPGA.
A key feature of CCSDS-123.0-B-2 is the new Hybrid Encoder option. At high bit-rates, the Hybrid Encoder encodes most samples using a family of codes that are equivalent to those used by the Sample-Adaptive Encoder of Issue 1, and thus has nearly identical performance. However, at low bit rates it has substantially better performance than the Issue 1 entropy encoders. For example, the Sample-Adaptive Encoder of Issue 1 cannot reach bit-rates lower than 1 bit-per-sample due to design constraints, while the Block-Adaptive Encoder may, but at a non-negligible bit-rate overhead.
The Hybrid Encoder option specified in CCSDS-123.0-B-2 is a modified version of the one originally used by the NASA FLEX entropy coder so that decoding proceeds in reverse order. This permits a more memory-efficient implementation than FLEX’s original coder, which was based on an interleaved entropy coding approach. The Hybrid Encoder includes codes equivalent to the length-limited GPO2 codes used by the Sample-Adaptive Encoder but it is augmented with an additional 16 variable-to-variable length “low-entropy” codes to provide better compression of low-entropy data. Such low-entropy data become more prevalent as increasing predictor quantization step sizes are used. The Hybrid Encoder adaptively switches between high and low entropy encoding methods on a sample-by-sample basis, using code selection statistics similar to those used by the Sample-Adaptive coder. A single output codeword from a low-entropy code may encode multiple samples, which allows obtaining lower compressed data rates than can be produced by the Sample-Adaptive Entropy coder.
In this contribution, we introduce a high-performance hardware implementation of the CCSDS-123.0-B-2 Hybrid Encoder targeting space-grade SRAM FPGA technology, described in portable VHDL RTL. The proposed Hybrid Encoder RTL architecture comprises 6 components at the top structural level: 1) an Adaptive Code Selection Statistics unit, 2) a High/Low Entropy Decision unit, 3) a High Entropy Encoder unit, 4) a Low Entropy Encoder, 5) a Codeword Combiner and 6) a Variable Length Code Packer unit. The proposed architecture achieves 1 sample per cycle when the high-entropy encoding method is selected and multiple cycles per sample when low-entropy coding is selected, while the deep pipeline enables very high clock frequencies. Moreover, the proposed architecture exploits the systolic design pattern to provide modularity and latency insensitivity in a elastic pipeline.
The implementation of the proposed architecture on a Xilinx Kintex Ultrascale XQRKU060 space-grade SRAM FPGA achieves state-of-the-art throughput performance of up to 354 MSamples/s (5.66 Gbps @ 16bpp) while occupying approximately 2.85% of device LUTs and 0.1% BRAMs of the FPGA resources. To the best of our knowledge, this is the first implementation of the CCSDS-123.0-B-2 Hybrid Encoder Implementation a space-grade SRAM FPGA.
