High Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression with CCSDS-123.0-B-1
| Monday, September 21, 2020 |
| 4:20 PM - 4:45 PM |
Speaker
Attendee26
National and Kapodistrian University of Athens
High Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression with CCSDS-123.0-B-1
Abstract Submission
Nowadays, hyperspectral imaging is recognized as a cornerstone remote sensing technology. Next generation, high-speed airborne and space-borne imagers, have increased resolution, resulting in an explosive growth in data volume and instrument data rate in the range of GPixels/s. This competes with limited onboard resources and bandwidth, making hyperspectral image compression a mission critical on-board processing task. At the same time, the "New Space" trend is emerging, where launch costs decrease, and agile approaches are exploited building smallsats using Commercial-Off-The-Shelf (COTS) parts. In this contribution, we introduce a high performance parallel implementation of the CCSDS-123.0-B-1 hyperspectral compression algorithm targeting SRAM FPGA technology. The architecture exploits image segmentation to provide robustness to data corruption and enables scalable throughput performance by leveraging segment-level parallelism. Furthermore, we exploit the capabilities of a COTS FPGA SoC device to optimize SWaP-C.
The architecture partitions a hyperspectral cube stored in a DRAM frame-buffer into segments, compressing them in parallel using a flexible software scheduler hosted in the SoC CPU and several compressor accelerator cores in the FPGA fabric. The input hyperspecral image is split across the Y-axis to form segments compressed independently with default prediction weights.The System-on-Chip is built around the CCSDS 123.0-B-1E IP core, and places a number of those compressors in parallel, scheduling configuration and data movement such that overall throughput scales linearly with the number of placed compressor cores. The software scheduler orchestrates a set of DMA controllers, to segment and transfer image data to the compressors at speed. The embedded ARM processors are used for control tasks only and can therefore be used to perform other preprocessing tasks such as data reduction or classification.
To evaluate the architecture, we perform on-chip benchmarking, instrumenting the control software to time and verify the compression operation of an AVIRIS sensor scene, under different levels of parallelism and segment height. A 5 core implementation demonstrated on a Zynq-7045 FPGA achieves throughput performance of 1387 Msamples/s (22.2 Gbps @ 16bpp), outperforms previous implementations in equivalent FPGA technology, allowing seamless integration with next-generation hyperspectral sensors. This implementation requires a Xilinx Zynq device and external memory, utilizing 91845 LUTs and 448 Block RAMs for a full SoC with 5 cores on the Zynq-7045 device.
The contribution first provides background on the CCSDS 123.0-B-1 algorithm as well as the trade-offs in pixel order, segmentation and considerations for COTS device usage. Benchmarks for various segmentation heights are presented to provide context on the compression performance overhead of segmentation. Then the proposed SoC architecture is described in detail including the parallelism scheme compared to other possible architectures, hardware and software design, as well as considerations on system integration in a payload data chain, consuming sensor data from device I/O and output compressed data towards a downlink. Finally, experimental results are presented, including FPGA implementation results, scaling overhead, technology limitations on scaling and on-chip benchmarked performance. Throughput performance is compared in detail with existing parallel hyperspectral compressors from the literature.
The architecture partitions a hyperspectral cube stored in a DRAM frame-buffer into segments, compressing them in parallel using a flexible software scheduler hosted in the SoC CPU and several compressor accelerator cores in the FPGA fabric. The input hyperspecral image is split across the Y-axis to form segments compressed independently with default prediction weights.The System-on-Chip is built around the CCSDS 123.0-B-1E IP core, and places a number of those compressors in parallel, scheduling configuration and data movement such that overall throughput scales linearly with the number of placed compressor cores. The software scheduler orchestrates a set of DMA controllers, to segment and transfer image data to the compressors at speed. The embedded ARM processors are used for control tasks only and can therefore be used to perform other preprocessing tasks such as data reduction or classification.
To evaluate the architecture, we perform on-chip benchmarking, instrumenting the control software to time and verify the compression operation of an AVIRIS sensor scene, under different levels of parallelism and segment height. A 5 core implementation demonstrated on a Zynq-7045 FPGA achieves throughput performance of 1387 Msamples/s (22.2 Gbps @ 16bpp), outperforms previous implementations in equivalent FPGA technology, allowing seamless integration with next-generation hyperspectral sensors. This implementation requires a Xilinx Zynq device and external memory, utilizing 91845 LUTs and 448 Block RAMs for a full SoC with 5 cores on the Zynq-7045 device.
The contribution first provides background on the CCSDS 123.0-B-1 algorithm as well as the trade-offs in pixel order, segmentation and considerations for COTS device usage. Benchmarks for various segmentation heights are presented to provide context on the compression performance overhead of segmentation. Then the proposed SoC architecture is described in detail including the parallelism scheme compared to other possible architectures, hardware and software design, as well as considerations on system integration in a payload data chain, consuming sensor data from device I/O and output compressed data towards a downlink. Finally, experimental results are presented, including FPGA implementation results, scaling overhead, technology limitations on scaling and on-chip benchmarked performance. Throughput performance is compared in detail with existing parallel hyperspectral compressors from the literature.
